The present disclosure relates to semiconductor device fabrication, and more particularly to a method of forming a silicon germanium channel on patterned silicon for use in hybrid channel complementary metal oxide semiconductor (CMOS) transistors.
As CMOS transistors scale down, methods of improving circuit performance are increasingly important. For certain technology node device requirements, it is necessary to use different channel materials for p-type FETs (pFETs) and n-type FETs (nFETs). For example, by taking advantage of high hole mobility of silicon germanium (SiGe) and high electron mobility of silicon (Si), performance of hybrid channel CMOS transistors with SiGe as the p-channel material and Si as the n-channel material can be greatly enhanced.
FIGS. 1 and 2 illustrate a conventional method for integrating SiGe and Si channel materials on a common substrate. As shown in FIG. 1, a silicon-on-insulator (SOI) substrate 100 having a top silicon layer 110 is first provided. A portion of the top silicon layer 110 located in a pFET region of the SOI substrate 110 is recessed by an anisotropic etch such as, for example, a timed reactive ion etch (RIE), while covering another portion of the top silicon layer 110 located in an nFET region of the SOI substrate 100 by a mask 120. Thereafter and as shown in FIG. 2, a pre-clean is carrier out prior to the epitaxial growth of SiGe to remove any native oxide from the recessed portion of the top silicon layer 110. A SiGe forming process is then performed to form a SiGe channel layer 130 over the recessed portion of the top silicon layer 110. The SiGe forming process may include a pre-bake clean process and a SiGe epitaxial grown process. The pre-bake clean process is typically performed at a relatively high temperature of about 800° C.
However, several problems are associated with the above described prior art integration process. First, since the RIE process is very sensitive to errors in the fabrication process, using RIE normally results in different Si recess depths at different locations in the pFET region. The recessed portion of the top Si layer 110 and the SiGe channel layer 130 subsequently formed thereon are not uniform due to the non-uniform recess. As a result, device characteristics vary as a function of device width, adversely increasing device design complication. In addition, recessed portion of the top Si layer 110 that remains in the pFET region is rather thin (e.g., the thickness of the recessed portion of the top Si layer 110 is typically less than 10 nm), the high pre-bake temperature can cause unwanted Si reflow, which results in corner rounding of the SiGe channel layer 130. The corner rounding often induces defects formation in the SiGe channel layer 130. Therefore, a method of forming a SiGe channel layer with improved uniformity and reduced defects for hybrid channel CMOS transistors remains needed.